Low-dropout (or LDO) voltage regulators are linear DC voltage regulators that are capable of operating with very low input-output differential voltages. The advantages of such regulators with respect to other types of voltage regulators include having a lower minimum operating voltage, higher power efficiency and lower heat dissipation.
A conventional LDO voltage regulator consists of an error amplifier and a pass field-effect-transistor or “pass-FET”. The error amplifier compares the output voltage (or a voltage derived therefrom) being generated by the LDO to a reference voltage and alters the conductivity of the pass-FET in order to drive the output voltage to the desired value.
Two important design parameters that must be considered when designing an LDO are the accuracy of the output voltage and the stability of the LDO, As with any circuit, the error amplifier of an LDO regulator has an associated transfer function which describes the frequency response of the circuit. The transfer function typically has a pole located at a particular frequency known as a corner frequency. Once the frequency of the lowest frequency or “dominant” pole has been reached, the gain of the circuit begins to decrease at a rate of 20 dB/decade (i.e. for every ten-fold increase in frequency, the gain drops by 20 dB). Any subsequent poles will then increase this rate by a further 20 dB/decade. Each pole will also introduce a 90 degree phase shift. Thus with two poles, the output is in antiphase (i.e. 180 degrees out of phase) with the input, which can cause the circuit to be unstable. In order for a circuit to be stable, the gain should drop to unity at a frequency lower than that of the second pole (i.e. the first “non-dominant” pole).
In a typical LDO circuit, the first pole is due to a (typically large) output capacitor while the second pole is due to the gate capacitance of the pass-FET. In some conventional LDO regulators a source follower stage is placed at the output of the error amplifier. Such a source follower stage drives the gate of the pass-FET and pushes the second pole to a relatively high frequency with a view to improving the stability of the LDO voltage regulator.
Typically, p-channel metal-oxide-semiconductor (PMOS) field-effect-transistors (pMOSFETs) are the technology of choice for implementing the pass-FET within the LDO in order to achieve a low drop-out voltage. At zero load currents, the gate terminal of the PMOS pass-FET has to be “pulled up” to the supply voltage or to the input voltage Vin, while at high load currents the gate terminal of the PMOS pass-FET has to be “pulled down” to ground. However, the Applicant has appreciated that there is an issue with these conflicting requirements—an n-channel metal-oxide-semiconductor (NMOS) source follower buffer cannot pull up the gate of the PMOS pass-FET to the supply voltage (or the input voltage Vin) and a PMOS source follower buffer cannot pull down the gate of the PMOS pass-FET to ground.
When viewed from a first aspect the present invention provides a low-dropout voltage regulator arranged to convert an input voltage to an output voltage, the low-dropout voltage regulator comprising:                an error amplifier circuit portion arranged to produce an error signal proportional to a difference between a sense voltage and a reference voltage, wherein the sense voltage is derived from the output voltage;        a pass field-effect-transistor connected to the input voltage;        a rail-to-rail buffer circuit portion connected between the input voltage and ground, said rail-to-rail buffer circuit portion comprising: a buffer input arranged to receive the error signal; a buffer output arranged to apply a buffer signal to the gate terminal of the pass field-effect-transistor, wherein said buffer signal is a buffered version of said error signal; and a resistive bypass arrangement connected between the buffer input and the buffer output.        
At least in preferred embodiments, the present invention provides a low-dropout voltage regulator for which it is not necessary to make a choice between the conflicting requirements referred to above; the pass field-effect-transistor (or “pass-FET”) can be pulled both up and down fully depending on whether the load current is high or not. With high load currents that cause the output voltage to drop, the sense voltage will also drop. This drop in the sense voltage may be detected by the error amplifier, and cause the buffer to drive the pass-FET such that additional current flows and increases the output voltage back to the desired level i.e. it may increase until the difference between the sense voltage and the reference voltage is sufficiently low for acceptable operation.
In some embodiments, when the load current is below a threshold, the rail-to-rail buffer circuit portion may be effectively disabled, with the output of the error amplifier being able to drive the pass-FET directly via the resistive bypass arrangement. Thus when the load current is low, the current consumption of the rail-to-rail buffer circuit portion may in some arrangements be kept to a minimum.
The bypass arrangement provides a mechanism for pulling up the gate terminal of the pass-FET. In some embodiments the bypass arrangement comprises a fixed resistor, and in preferred embodiments the fixed resistor is constructed from a field-effect-transistor. While the resistance of the fixed resistor is typically set at a particular value chosen when designing the circuit, it is envisaged that the resistance of the fixed resistor could be variable. Having a variable resistance may provide the benefit of being able to vary an offset of the error amplifier (e.g. by driving the resistance to a high value when the load current is high).
In at least some preferred embodiments the pass field-effect-transistor comprises a p-channel metal-oxide-semiconductor field-effect-transistor (pMOSFET), wherein the source terminal of the pass field-effect-transistor is connected to the input voltage. In some such embodiments, the error amplifier is arranged such that the sense voltage is applied to a non-inverting input of said error amplifier and the reference voltage is applied to an inverting input of said error amplifier. In such embodiments, the error amplifier is arranged to detect if the sense voltage has fallen to the reference voltage and if so decrease its output voltage such that the conductivity of the pMOS pass-FET increases.
However, it will be appreciated that in alternative embodiments, the pass field-effect-transistor comprises an n-channel metal-oxide-semiconductor field-effect-transistor (nMOSFET), wherein the drain terminal of the pass field-effect-transistor is connected to the input voltage. In some such embodiments, the error amplifier is arranged such that the reference voltage is applied to a non-inverting input of said error amplifier and the sense voltage is applied to an inverting input of said error amplifier. In such embodiments, the error amplifier is arranged to detect if the sense voltage has fallen to the reference voltage and if so increase its output voltage such that the conductivity of the nMOS pass-FET increases.
While the output voltage could be compared to the reference voltage directly, in some embodiments the pass field-effect-transistor is connected in series with a potential divider circuit portion comprising at least first and second resistors, wherein the sense voltage comprises the voltage at a node between said first and second resistors. Thus it will be appreciated that in such embodiments the potential divider circuit portion acts as a feedback for the error amplifier. The sense voltage taken from this node will be proportional to the output voltage and will depend on the ratio between the resistance of the first resistor and the resistance of the second resistor. In some embodiments, the resistance of the first resistor and/or the resistance of the second resistor is variable. This provides a way of varying the reference voltage, e.g. by using a programmable resistance that can be varied using a controller.
There are a number of buffer topologies which may be used to implement the rail-to-rail buffer circuit portion described hereinabove, however in some preferred embodiments the rail-to-rail buffer circuit portion comprises:                an input field-effect-transistor, wherein the buffer input comprises the gate terminal of said input field-effect-transistor;        an output field-effect-transistor having its source terminal connected to the source terminal of the input field-effect-transistor, and its gate and drain terminals connected to the gate terminal of the pass field-effect-transistor;        a current source arrangement connected to the source terminals of the input and output field-effect-transistors; and        a current sink arrangement connected to the drain terminal of the input and output field-effect-transistors.        
In preferred embodiments, the input field-effect-transistor comprises a p-channel field-effect-transistor. In some potentially overlapping embodiments, the output field-effect-transistor comprises a p-channel field-effect-transistor.
In some such embodiments, the current source arrangement comprises a current mirror including first and second source mirror field-effect-transistors and a current source, wherein:                the gate terminal of the first source mirror field-effect-transistor is connected to the drain terminal of the first source mirror field-effect-transistor, the gate terminal of the second source mirror field-effect-transistor, and the current source which is further connected to ground;        the source terminals of the first and second source mirror field-effect-transistors are connected to the input voltage; and        the drain terminal of the second source mirror field-effect-transistor is connected to the source terminals of the input and output field-effect-transistors. In a preferred set of such embodiments, said first and second mirror field-effect-transistors comprise p-channel field-effect-transistors.        
In some potentially overlapping embodiments, the current sink arrangement comprises first and second sink field-effect-transistors wherein;                the gate terminal of the first sink field-effect-transistor is connected to the drain terminal of the first sink field-effect-transistor, the gate terminal of the second sink field-effect-transistor, and the drain terminal of the input field-effect-transistor;        the drain terminal of the second sink field-effect-transistor is connected to the drain and gate terminals of the output field-effect-transistor and the gate terminal of the pass field-effect-transistor. In a preferred set of such embodiments, said first and second sink field-effect-transistors comprise n-channel field-effect-transistors.        
The first and second sink field-effect-transistors should be connected to a sufficiently low voltage in order to pull down the gate terminal of the pass-FET. In a preferred set of embodiments, the source terminals of the first and second sink field-effect-transistors are connected to ground.
While it will be appreciated that there are a number of different arrangements suitable for implementing an error amplifier known in the art per se, in some preferred embodiments the error amplifier comprises an operational amplifier. Operational amplifiers or “op-amps” are DC-coupled, high gain voltage amplifiers typically provided with a differential input and a single-ended output, wherein the voltage at the output is proportional to a difference between the voltages presented at the differential input. The actual gain of the op-amp will depend on any negative bypass arrangement together with the specific topology of the circuit in which the op-amp is being used.